For a long time, in order to achieve a higher chip density, a faster operating speed and a lower power consumption, a feature size of a metal-oxide-semiconductor field effect transistor (MOSFET) is continuously scaled down, and currently has reached an ultra deep submicron level and a nanometer level. However, a serious challenge is an emergence of a short-channel effect, such as a subthreshold voltage roll-off (Vt roll-off), a drain-induced barrier lowering (DIBL) and a source-drain punch through, thus increasing a subthreshold slope of the MOSFET and significantly increasing an off-state leakage current. Therefore, a performance of the MOSFET may be deteriorated.
A TFET (tunneling field effect transistor) is a quantum mechanical device based on a tunneling effect of a carrier, and has a weaker short-channel effect and a smaller leakage current compared with a conventional MOS transistor. The structure of a TFET device is based on a metal-oxide-semiconductor gated P-I-N diode. FIG. 1 is a cross-sectional view of a conventional TFET with an N-type channel. Particularly, the conventional TFET comprises: a substrate 1100′; an insulating layer 1200′ formed on the substrate 1100′; a P-doped source region 1000′, an N-doped drain region 2000′ and a channel region 3000′ between the P-doped source region 1000′ and the N-doped drain region 2000′ formed on the insulating layer 1200′; and a gate stack 4000′ formed on the channel region 3000′. The channel region 3000′ may be intrinsically doped, lightly P-doped or lightly N-doped. Preferably, the channel region 3000′ is lightly N-doped. That is, the N-type TFET preferably has a P+/N−/N+ structure. The gate stack 4000′ comprises a gate dielectric layer formed on the channel region 3000′ and a gate conductive layer formed on the gate dielectric layer.
When the TFET is turned off, that is, no gate voltage is applied, a junction formed between the source region 1000′ and the drain region 2000′ is a reverse biased diode, and a potential barrier created by the reverse biased diode is greater than that created by a conventional complementary MOSFET, thus greatly reducing a subthreshold leakage current and a direct tunneling current of the TFET even if a channel length is very short. When a voltage is applied to a gate in the TFET, under an action of a field effect, an electron channel may be formed in the channel region 3000′. Once an electron concentration in the channel region 3000′ is degenerated, a tunneling junction will be formed between the source region 1000′ and the channel region 3000′, and a tunneling current generated by carrier tunneling will pass through the tunneling junction. From the perspective of an energy band, with the tunneling field effect transistor based on a gate controlled P-I-N diode, a tunnel length of a PN junction formed between the source region 1000′ and the channel region 3000′ is adjusted by controlling the voltage of the gate. Therefore, the tunneling field effect transistor is a transistor with a very low leakage current. As a result, when the tunneling field effect transistor works, a voltage of a power supply may be reduced to 0.5 volts or even 0.1 volts, and consequently the tunneling field effect transistor may be applied to a circuit chip with a low power consumption. However, because of being limited by a band-to-band tunneling probability, a driving current of a conventional tunneling field effect transistor is lower than that of a conventional MOSFET device by 2 to 4 orders of magnitude. Therefore, in order to improve a performance of an integrated circuit chip integrated with a tunneling field effect transistor, the driving current of the tunneling field effect transistor needs to be increased, and the subthreshold slope needs to be reduced. Currently, there are two following problems to be solved. On the one hand, in order to reduce the subthreshold slope, a doping concentration gradient of the PN junction formed between the source region and the channel region needs to be more steep, however, the conventional tunneling field effect transistor with a planar structure may not meet this requirement, thus largely increasing a difficulty of process flows and a cost. On the other hand, when the driving current of the tunneling field effect transistor is increased using narrow band-gap materials, the off-state leakage current of the device will be increased, thus deteriorating the performance of the transistor.